1. Field of the Invention
An aspect of the present invention relates to a semiconductor memory device and a method for manufacturing the same.
2. Description of the Related Art
NAND-type nonvolatile memories have a structure in which a plurality of memory cell transistors formed on element regions of a semiconductor substrate is serially connected to each other, and select gate transistors are arranged on both sides of the plurality of memory cell transistors. To simplify the manufacturing process steps for the NAND-type nonvolatile memories, the memory cell transistors and the select gate transistors are fabricated simultaneously (see JP-A-2002-176114, for example).
In the fabrication method, a first electrode layer is formed on a memory cell region and a select gate region of the semiconductor substrate. Then, an inter-electrode insulating film is formed on the first electrode layer. The inter-electrode insulating film of the select gate region is partially removed to form an opening that exposes a lower gate electrode layer, while the inter-electrode insulating film of the memory cell region is not removed. Next, a second electrode layer is formed on the semiconductor substrate so that, in the memory cell region, the first and second electrode layers are electrically isolated, and so that, in the select gate region, the first and second electrode layers are electrically connected through the opening. With this, a memory cell gate electrode having a double-layer gate structure including a floating gate electrode layer and a control gate electrode layer is formed in the memory cell region. Meanwhile, a select gate electrode having a single-layer gate structure in which a lower gate electrode layer and an upper gate electrode layer are electrically connected via the opening is formed in the select gate region.
Through the forming of the opening that exposes the lower gate electrode layer in the select gate region, a natural oxide film is formed on the exposed portion of the lower gate electrode layer, causing a conduction failure between the upper gate electrode layer and the lower gate electrode layer. In order to remove the natural oxide film, the exposed portion of the lower gate electrode layer is cleaned with hydrofluoric acid. However, at the time of removing the natural oxide film from the surface of the lower gate electrode layer, the portion of the element isolation insulating film exposed from the opening is also removed. Thus, there is a possibility that the upper surface of the element isolation insulating film exposed from the opening becomes lower than the surface of the semiconductor substrate. As a result, there is a fear that the lower gate electrode layer of the select gate region and the semiconductor substrate are short-circuited.
In the NAND-type nonvolatile memories, there is a problem, known as inter-cell interference, which is accompanied by miniaturization. To suppress the inter-cell interference, it is effective to decrease the thickness of the floating gate electrode layer of the memory cell transistor (see IEEE Non-Volatile Semiconductor Memory Workshop 2006, pages 9 to 11, for example).
However, when the thin floating gate electrode layer is subjected to the hydrofluoric acid cleaning, the following problems may arise. The removal of the inter-electrode insulating film in the select gate region is carried out on the element isolation insulating film as well as on the lower gate electrode layer. Therefore, the element isolation insulating film where the inter-electrode insulating film is removed is also removed by the hydrofluoric acid cleaning. Here, the element isolation insulating film is formed so as to be lower than the upper surface of the floating gate electrode layer in order to increase the capacitive coupling ratio between the control gate electrode layer and the floating gate electrode layer of the memory cell transistor in the memory cell region. Also, the element isolation insulating film is formed so as to protrude from the surface of the semiconductor substrate in order to prevent the control gate electrode layer of the memory cell transistor and the upper gate electrode layer of the select gate transistor from being short-circuited to the semiconductor substrate in the memory cell region and in the select gate region. In this case, if the thickness of the floating gate electrode layer is decreased in order to suppress the inter-cell interference, the element isolation insulating film is over-etched by the hydrofluoric acid cleaning, decreasing the amount of protrusion and thus lowering the upper surface of the element isolation insulating film to be lower than the surface of the semiconductor substrate. As a result, there is a fear that the lower gate electrode layer of the select gate region and the semiconductor substrate are short-circuited.